1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a dynamic random access memory (DRAM) for generating internal voltage.
2. Description of the Background Art
In general, semiconductor devices are roughly classified into volatile memories represented by RAM and non-volatile memories represented by ROM. Volatile memories are further classified roughly into DRAMs and static random access memories (SRAMs). A DRAM activates operation within a chip by inputting a row address strobe signal (hereinafter referred to as RAS) and a column address strobe signal (hereinafter referred to as CAS). In RAS and CAS, H (logical high) is a stand-by state and L (logical low) is an active state. By activation of RAS, an input address is incorporated as a row address. By activation of CAS, the input address is incorporated as a column address.
FIGS. 15A and 15B are timing charts illustrating how RAS and CAS are input when in a normal operation mode. FIG. 15A is for normal input of RAS and CAS when row address and column address are incorporated, while FIG. 15B is for input of RAS and CAS when only row address is incorporated.
Referring to FIG. 15A, when row and column addresses are incorporated, RAS is activated first so as to incorporate the row address, and then CAS is activated so as to incorporate the column address.
Referring to FIG. 15B, when only row address is incorporated, activation is effected only on RAS while CAS is maintained at a standby state so that only row address is incorporated.
In both cases of FIGS. 15A and 15B, N word lines in the memory array are activated within the chip, corresponding to the row address incorporated. N is a constant determined by the configuration of the chip. Usually, N=1, 2, 4, 8, 16, and so on.
DRAMs further employ an inputting method called CBR mode (CAS-Before-RAS-mode) which is used when performing a refresh operation.
FIG. 16 is a timing chart for illustrating the state of input during CBR mode.
Referring to FIG. 16, CAS is activated before activation of RAS, in an order opposite to that of FIG. 15A. When in CBR mode, neither of row address and column address is externally incorporated to the chip and M.times.N word lines on the memory array is activated corresponding to internal row address generated at an address counter within the chip in synchronization with RAS. Here, this N is the same number as the N mentioned above. Usually, M=1, 2, 4, 8, 16 and so on, also determined by the configuration of the chip.
FIG. 17 shows an example of a memory array 1600 included in a conventional DRAM in general.
Referring to FIG. 17, memory array 1600 is divided into rectangular memory blocks #0-15 each provided with one side having a length of 1 word line, (that is, 1WL length) and another side having a length of 1 bit line (that is, 1BL length). Memory blocks #0-15 each include word lines WL0-15, respectively (although WL1, 3, 5, 7, 9, 11, 13, and 15 are not shown).
In normal operation mode shown in FIGS. 15A and 15B, activation is effected on, for example, four word lines WL0, 4, 10, 14. Meanwhile, in CBR mode, activation is effected on a total of eight word lines, that is, word lines WL0, 4, 10, 14 plus word lines WL2, 6, 8, 12. Accordingly, the example shown in FIG. 17 illustrates the case in which N=4 and N=2.
The word lines described above are at GND when at the standby state, and is charged to a potential Vpp which is higher than power supply potential Vcc when at an activated state. When at the normal operation mode shown in FIGS. 15A and 15B, the charge Q (Normal) consumed per cycle (i.e., cycle in which RAS is activated one time) is expressed as Q (Normal)=N.times.Cw.times.Vpp, where Cw is the capacitance of one word line.
In addition, as shown in FIG. 17, N=4 memory blocks #0, 4, 10, 14 are operating at the normal operation mode shown in FIGS. 15A and 15B. In particular, the bit lines of the above-described memory blocks are being charged or discharged and sense amplifiers corresponding to these memory blocks are in operation. Meanwhile, at the CBR mode shown in FIG. 16, a total of N.times.M=8 memory blocks, that is, memory blocks #0, 4, 10, 14 plus memory blocks #2, 6, 8, 12 are in operation. The above-described memory blocks have their bit lines charged or discharged while the sense amplifiers corresponding to these memory blocks are in operation.
However, in the CBR mode shown in FIG. 16, charge Q (CBR) which is consumed within one cycle is expressed as Q (CBR)=N.times.M.times.Cw.times.Vpp and is charged by Vpp power supply as in the normal operation mode. Accordingly, the amount of charge consumed in CBR mode is M times as large as the amount of charge consumed in normal mode.
Furthermore, referring to FIG. 8 in which a partial configuration of a memory cell included in a DRAM 100 is shown, a transfer gate control line TG1 is also sometimes charged to a potential Vpp' which is higher than power supply potential Vcc at Vpp power supply or at a node different from Vpp. Here, charge Q (Normal) consumed within one cycle in normal operation mode is expressed as Q (Normal)=N.times.Ctg.times.Vpp (or Q (Normal)=N.times.Ctg.times.Vpp') where Ctg is the capacitance of one transfer gate control line, while in CBR mode, Q (CBR)=N.times.M.times.Ctg.times.Vpp (or Q (CBR)=N.times.M.times.Ctg.times.Vpp') so that the amount of charge consumed from Vpp power supply (or Vpp' power supply) is M times as large as the amount of charge consumed in the normal operation mode.
This internal power supply potential Vpp (or Vpp') is generated at Vpp (or Vpp') generating circuit.
FIG. 18 is a circuit diagram showing a general boost pump 1800 employed as a Vpp generating circuit.
Referring to FIG. 18, when capacitance Cp of pump capacitor 1803 included in a boost pump 1800 is used, the charge which can be generated within one cycle by Vpp generating circuit will be expressed as Q=(2 Vcc-Vpp).times.Cp. Accordingly, when Vpp generating circuit is designed to accommodate the normal operation mode, the charge required for charging the word line would not be sufficient when CBR mode is entered.
In addition, this memory array is formed on a P type semiconductor substrate having a potential Vbb which is lower than GND. As already mentioned, the number of the memory blocks operating at CBR mode is M times as large as the number of memory blocks operating at normal operation mode. Accordingly, when the bit line is charged or discharged, the amount of the substrate current to the P type semiconductor substrate at the sense amplifier portion during CBR mode is M times as large as that of the substrate current obtained in the normal operation mode. The internal power supply potential Vbb is generated at Vbb generating circuit, and charge which can be generated by Vbb generating circuit within one cycle is predetermined as in the above-described Vpp generating circuit. When Vbb generating circuit is designed to accommodate the normal operation mode, the substrate current is increased when CBR mode is entered such that the Vbb potential may be made shallower (i.e., higher) than the prescribed potential.